DoD Enterprise DevSecOps Reference Design from the DoD CIO – A Summary Content referenced from: https://dodcio.defense.gov/Portals/0/Documents/DoD%20Enterprise%20DevSecOps%20Reference %20Design%20v1.0_Public%20Release 0_Public%20Release.pdf?ver=2019-09-26-115824-583 DevSecOps – Defined by DoD CIO DevSecOps is an organizational software engineering culture and practice that aims at unifying software development (Dev) sidecar container CSIAC Webinars - DoD Enterprise DevSecOps Initiative – Nicolas Chaillan presenting https://www.csiac.org/podcast/dod-enterprise-devsecops-initiative/ DoD Centralized Container Source Code

Public Release; Distribution Unlimited. 14-0391ii Executive Summary The Department of Defense (DoD) needs an acquisition framework for information technology (IT) that can keep pace with rapidly changing can help the DoD to transform IT acquisition by delivering capabilities faster and responding more effectively to changes in operations, technology, and budgets. This guide provides DoD acquisition professionals adoption across the DoD and other federal agencies. Agile practices enable the DoD to achieve reforms directed by Congress and DoD Acquisition Executives. DoD Instruction 5000.02 (Dec 2013) heavily emphasizes

programming • Modules • 2000s • Template metaprogramming • Concurrency • 2020s • ??? 3What is DoD about? • DoD (“Data oriented design”) • Not about cache lines, nor struct layout (at its core) • From wikipedia: 4Minimalist definition of DoD 𝐷𝑎𝑡𝑎!"#$"# = 𝐹(𝐷𝑎𝑡𝑎%&$"#) Transformation Input Data Output Data Specific transformation Previous transformation Next transformation 5How DoD is used in actual ChatGPT… 7 That’s cool, but it won’t get us very far…How can we improve it? (second try) • At its core DoD is just: 𝐷𝑎𝑡𝑎!"#$"# = 𝐹(𝐷𝑎𝑡𝑎%&$"#) • … With a heavy focus on the data. • What if we looked

Cost Estimation  Cost estimation in an Agile environment is challenging  The challenge within DoD is often a resistance to allocate budget for a program until all the requirements are fully defined

Malware Research # @ Endgame 0x40200B Malware Research # @ Fireeye 0x40201A Computer Forensics # @ DoD PREVIOUS 0x40D021 Blackhat, RSA, DEFCON, 0x40D02B 44Con, CanSecWest 0x40D02E BsidesSF, WiCys 0x40D032

carry much more semantic information implicitly. Here, think of examples where a single bytecode instruction might do a full matrix multiplication, or change the prototype of a class. There are much higher architecture on another architecture. Dynamic binary translation: execute the program from one Instruction Set Architecture in another (or the same) ISA, performing the translation dynamically. In other dynamic optimization system that is capable of transparently improving the performance of a native instruction stream as it executes on the processor. Focus its efforts on optimization opportunities that

www.linkedin.com/in/alexdathskovsky INO Execution • instruction fetch • if operands available execute it if not fetch them • The instruction is executed by the functional unit • The functional unit Scheduling • instruction fetched • instruction dispatched to instruction que • The instruction waits in the que untils its input operand are available • if operands available instruction is allowed to to leave the queue before other instructions • The instruction is issued to a functional unit • Only if all older instructions have completed the operation the result is written to register fileAlex

● Data dependency: a = (v1 + v2)*(v1 – v2) ● Pipeline increases CPU utilization ● Multiple instruction streams run in parallel – Dependencies within each stream – No data dependencies between streams executed ● Conditional jumps (branches) disrupt that order ● CPU must wait until it knows which instruction to fetch next load:v1[i] load:v2[i] cmp[i]:v1[i]>v2[i] jump if true a[i]:a+=v2[i] jump a[i]:a+=v1[i] executed ● Conditional jumps (branches) disrupt that order ● CPU must wait until it knows which instruction to fetch next load:v1[i]...v3[i] cmp[i]:v3[i]==0 jump if true a[i]:a+=v1[i]+v2[i] jump a[i]:a+=v1[i]*v2[i]

atomic topFrame; AsyncStackRoot* nextRoot; frame_ptr stackFramePtr; instruction_ptr returnAddress; };So what was that magic*? struct AsyncStackRoot { atomic atomic topFrame; AsyncStackRoot* nextRoot; frame_ptr stackFramePtr; instruction_ptr returnAddress; };So what was that magic*? struct AsyncStackRoot { atomic topFrame; nextRoot; frame_ptr stackFramePtr; instruction_ptr returnAddress; }; struct AsyncStackFrame { AsyncStackFrame* parentFrame; instruction_ptr instructionPointer; AsyncStackRoot* stackRoot;

completely memory mapped • Only 8080’s set of registers • Z80’s extended bit manipulation instruction set • Some aditional new instructionsCPU Block DiagramMemory & Memory mapped access • 8 KiB of the CPU. Emulators with T-cycle accuracy simulate the exact number of clock ticks for every instruction, providing the highest level of timing precision. • M-Cycle: Memory Cycle. An M-cycle represents represents a higher-level unit of time used by the Game Boy's CPU for executing instructions. Each instruction takes a specific number of M-cycles, with each M-cycle typically equating to 4 T-cycles. 21T-Cycle