elsewhere. This simple ATOM program instruments all of an (already compiled) program’s load and store instructions, adding a call to a function before each. Therefore, ATOM disassembles a program, instruments memory), or simulate details such as non-architectural state (shadow registers, etc), timing of instructions, caches, memory, etc. This is very slow to interpret. Embra is the first machine simulator to from original source to IR. Also, some IRs have easier to analyze structure Such as: * “Which instructions use this result?” * “What is the control flow that leads here?”— 2006 Design of the Java HotSpot

reliable on modern CPUs. ● We’ll use simple examples, so that we can just compare the number of instructions generated by a compiler. 13“… machine code … can range from 10s to 100s of megabytes in size sum_12_3 9 instructions 7 instructions 9 instructions sum_13_2 10 instructions 8 instructions 10 instructions sum_23_1 11 instructions 9 instructions 12 instructions sum_21_3 12 instructions 10 instructions instructions 12 instructions 130sum_12_3 sum_13_2 push rbx mov ebx, edx call sum(int, int) mov esi, ebx pop rbx mov edi, eax jmp sum(int, int) push rbx mov ebx, esi mov esi, edx call sum(int

Address Offset 32-bits ● For transparent 🫥 functions needing only 3 unwind instructions. ● Saves memory 122ARM unwind instructions Instruction Explanation 00xxxxxx vsp = vsp + (xxxxxx << 2) + 4. Covers (for example, out of a cleanup) 123 Note: Instructions are in 8-bit segments Limit is 7 bytes 3 bytes typicallyARM Personality Data: Unwind Instructions SU16 = Short Personality with 16-bit scopes function. reserved Personality Index Can be 0, 1, or 2 on ARM 124ARM Personality Data: Unwind Instructions LU16 = Long Personality with 16-bit scopes (always 8-bytes to 12-bytes) LU32 = Long Personality

instruction is allowed to leave the queue before other instructions • The instruction is issued to a functional unit • Only if all older instructions have completed the operation the result is written executed out of order iff there is no dependency on previous instructions • ready instructions can execute before earlier instructions that are stalledAlex Dathskovsky | alex.dathskovsky@speedata.io must define specific instructions called synchronizing instructions, which provide a way to coordinate different processors (equivalently, threads) ● Programs use those instructions to create a “happens

platform dependent though. 39Processor (core) 40 Instructions Data CoreInstruction fetch 41 Fetch L1I • Gets next block of (partial) instructions • Linear fetch • Incoming branch • Instruction complex • High cost of errorInstruction decoding 43 Branching Fetch Decode L1I • Multiple instructions get decoded in parallel • Even for variable length encoding • Not that complex in HW domain sequential • Can be physically parallel • HW is inherently parallel • Myth: decoding variable length instructions is: - Complex - Serial - Slow • Fetch block size • Linear fetch vs incoming branch 44Instruction

ta_tamer_cpp")); let conan_instructions = ConanInstall::with_recipe(&data_tamer_cpp) .build("missing") .run() .parse(); let conan_includes = conan_instructions.include_paths(); let toolchain_file cmake")); build.rs 39let conan_instructions = ConanInstall::with_recipe(&data_tamer_cpp) .build("missing") .run() .parse(); let conan_includes = conan_instructions.include_paths(); let toolchain_file data_tamer_lib_path.display() ); println!("cargo:rustc-link-lib=static=data_tamer"); conan_instructions.emit(); Ok(()) } build.rs 42#pragma once #include namespace DataTamer { template

pipeline code: a+=(v1[i]>v2[i])?v1[i]:v2[i] ● Pipelining relies on a continuous stream of instructions ● Instructions are fetched, decoded, and executed ● Conditional jumps (branches) disrupt that order (v3[i]) ? (v1[i]+v2[i]) : (v1[i]*v2[i]) ● Pipelining relies on a continuous stream of instructions ● Instructions are fetched, decoded, and executed ● Conditional jumps (branches) disrupt that order Sometimes the compiler will do a branchless transformation for you – Often using “conditional move” instructions (they are not branches) ● Compiler’s branchless optimization is usually better than yours ●

Cycle. An M-cycle represents a higher-level unit of time used by the Game Boy's CPU for executing instructions. Each instruction takes a specific number of M-cycles, with each M-cycle typically equating Cycle. An M-cycle represents a higher-level unit of time used by the Game Boy's CPU for executing instructions. Each instruction takes a specific number of M-cycles, with each M-cycle typically equating operand always a register! SUB reg, reg SUB reg, address SUB reg, constantWatch out for math instructions MUL and DIV! MUL reg DIV reg MUL address DIV address MUL constant DIV constant Target of MUL

Tape Capacity ~10ms ~100ms 10-100µs ~80-100ns 1-10ns ~0.1ns Volatile Memory Load/Store Instructions Cache Line Granularity Non-Volatile Memory I/O Commands Block Granularity Figure 1: Traditional Memory Hierarchy ~10ms ~100ms 10-100µs ~80-100ns 1-10ns ~0.1ns Volatile Memory Load/Store Instructions Cache Line Granularity Non-Volatile Storage I/O Commands Block Granularity CPU Registers SSD Hard Disk Drives (HDD) Tape Persistent Memory < 1µs Non-Volatile Storage Load/Store Instructions Cache Line Granularity Capacity Figure 2: New Memory Hierarchy [1] A Persistent Hash Map for

Basics: Functional Programming in C++ CppCon 2024-09-19 1Imperative Programming Definition Specify instructions that manipulate state in order to achieve a goal. Jonathan Müller — @foonathan Back to Basics: Basics: Functional Programming in C++ CppCon 2024-09-19 2Imperative Programming Definition Specify instructions that manipulate state in order to achieve a goal. C and C++ Jonathan Müller — @foonathan Back Basics: Functional Programming in C++ CppCon 2024-09-19 2Imperative Programming Definition Specify instructions that manipulate state in order to achieve a goal. C and C++ CPU Jonathan Müller — @foonathan