Cross-Platform Floating-Point Determinism Out of the Boxwith floating-point fallback Mykhailo Borovyk 🇺🇦 mbo@6it.dev Implementing support for RISC-V, including inline-asm Vladyslav Merais 🇺🇦 vmer@6it.dev Overall idea, and Insisting that 14/163 0/489 MSVC/x64 17/163 17/163 14/163 0/489 Apple Clang/ARM64 23/163 23/163 14/163 0/489 GCC/RISC-V 25/163 24/163 14/163 0/489 Tests: determinism failed / all testsPerformance: dmath&geometry tests_ 4.83x 1.89x 1.87x 1.33x 2.20x 1.31x Apple-Clang/ ARM64 5.54x 2.43x 3.09x 1.32x 2.47x 2.39x GCC/RISC-V 3.97x 3.07x 1.55x 1.10x 1.09x 1.10x Process-wide Deoptimizations — — No LTO — No fast-math, no0 码力 | 31 页 | 3.88 MB | 6 月前3
jsc::chunk_evenly Range Adaptor for Distributing Work Across Tasks32bit 64bit 32bit 64bit Xx86 ARM RISC-V Xx86 ARM RISC-V (6) Following zero-overhead principle auto func (std: :Tanges: remainder ]}; 了] 了 y 一Range adaptorfor dlstributing work across tasks (CZ) ASM comparison > GCC RISC-V 64-bit assembly manual_loop(long,long): jsc-chunk_evenly (long,long): addiji sp0 码力 | 1 页 | 1.38 MB | 6 月前3
Performance Engineering: Being Friendly to Your Hardwareuint64_t v = 0x123456789abcdef0; 48 x86 movabs r10, 0x123456789abcdef0 49 ba f0 de bc 9a 78 56 34 12 RISC-V li a5, 305418240 addi a5, a5, 1657 li a0, -1698897920 slli a5, a5, 32 addi a0, a0, -272 add uint64_t v = 0x123456789abcdef0; 49 x86 movabs r10, 0x123456789abcdef0 49 ba f0 de bc 9a 78 56 34 12 RISC-V li a5, 305418240 addi a5, a5, 1657 li a0, -1698897920 slli a5, a5, 32 addi a0, a0, -272 add uint64_t v = 0x123456789abcdef0; 50 x86 movabs r10, 0x123456789abcdef0 49 ba f0 de bc 9a 78 56 34 12 RISC-V li a5, 305418240 addi a5, a5, 1657 li a0, -1698897920 slli a5, a5, 32 addi a0, a0, -272 add0 码力 | 111 页 | 2.23 MB | 6 月前3
cppcon 2021 safety guidelines for C parallel and concurrencyCanada TC22/SC32 Electrical and electronic components (SOTIF) ● Chair of UL4600 Object Tracking ● RISC-V Datacenter/Cloud Computing Chair ● http://wongmichael.com/about ● C++11 book in Chinese: https://www Machine Learning WG3 Trustworthiness • ITC22/SC32 SOTIF WG8 SOTIF, WG13, WG14 • SAE ORAD • UL4600 • RISC-V Safety/Security • Misra: checkable rules only • Autosar C++ Guidelines: a mix of meta guidelines0 码力 | 52 页 | 3.14 MB | 6 月前3
Multi Producer, Multi Consumer, Lock Free, Atomic Queuequeue paper 4. Multiple read of the same entry - reads count 5. Porting to other platforms Windows, RISC-V, Arm 6. Performance improvement 51 CppCon 2024 | Erez Strauss | Lockfree, MPMC Queue https://github0 码力 | 54 页 | 886.12 KB | 6 月前3
Heterogeneous Modern C++ with SYCL 2020Canada TC22/SC32 Electrical and electronic components (SOTIF) ● Chair of UL4600 Object Tracking ● RISC-V Datacenter/Cloud Computing Chair ● http://wongmichael.com/about ● C++11 book in Chinese: https://www0 码力 | 114 页 | 7.94 MB | 6 月前3
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