The RISC-V Reader:
An Open Architecture AtlasFirst Edition, 1.0.0 - 2021made the design decisions they did. —Megan Wachs, PhD, SiFive Engineer Category Name Fmt RV32I Base Category Name Fmt RV mnemonic Shifts Shift Left Logical R SLL rd,rs1,rs2 Trap CSS B CIW U CL J CS CB CJ RISC-V Integer Base (RV32I/64I), privileged, and optional RV32/64C. Registers x1-x31 and the PC are 32 bits wide in RV32I and 64 in RV64I (x0=0). RV64I adds 12 instructions Reference Card xx +RV64I Base Integer Instructions: RV32I and RV64I RV Privileged Instructions SRLI rd,rd,imm BEQ rs1',x0,imm BNE rs1',x0,imm JAL0 码力 | 232 页 | 5.16 MB | 1 年前3
共 1 条
- 1













