In Praise of The RISC-V Reader This timely book concisely describes the simple, free and open RISC-V ISA that is expe- riencing rapid uptake in many different computing sectors. The book also contains well-worn reference guide for many RISC-V practitioners. —Professor Krste Asanovi´c, University of California, Berkeley, one of the four architects of RISC-V I like RISC-V and this book as they are elegant—brief set architectures This handy little book effortlessly summarizes all the essential elements of the RISC-V Instruction Set Architecture, a perfect reference guide for students and practitioners alike. —Professor

labs/cs630-qemu-lab and use it in Linux Lab directly – https://tinylab.org/cs630-qemu-lab • RVOS Lab – Learning RISC-V OS course, merged in Linux Lab Disk – Download it to src/examples and use it in Linux Lab directly com/tinylab/gui-lab • RISC-V Linux – Learning RISC-V Linux kernel, merged in Linux Lab Disk – Download it to src/examples and use it in Linux Lab directly – https://gitee.com/tinylab/riscv-linux • RISC-V Lab – Learning Learning embedded RISC-V software development，merged in Linux Lab Disk for RISC-V – https://gitee.com/tinylab/riscv-lab • ARM Lab – Learning embedded ARM software development，merged in Linux Lab Disk

labs/cs630-qemu-lab and use it in Linux Lab directly – https://tinylab.org/cs630-qemu-lab • RVOS Lab – Learning RISC-V OS course, merged in Linux Lab Disk – Download it to src/examples and use it in Linux Lab directly com/tinylab/gui-lab • RISC-V Linux – Learning RISC-V Linux kernel, merged in Linux Lab Disk – Download it to src/examples and use it in Linux Lab directly – https://gitee.com/tinylab/riscv-linux • RISC-V Lab – Learning Learning embedded RISC-V software development，merged in Linux Lab Disk – https://gitee.com/tinylab/riscv-lab • ARM Lab – Learning embedded ARM software development，merged in Linux Lab Disk – https://gitee

labs/cs630-qemu-lab and use it in Linux Lab directly – https://tinylab.org/cs630-qemu-lab • RVOS Lab – Learning RISC-V OS course, merged in Linux Lab Disk – Download it to src/examples and use it in Linux Lab directly com/tinylab/gui-lab • RISC-V Linux – Learning RISC-V Linux kernel, merged in Linux Lab Disk – Download it to src/examples and use it in Linux Lab directly – https://gitee.com/tinylab/riscv-linux • RISC-V Lab – Learning Learning embedded RISC-V software development，merged in Linux Lab Disk – https://gitee.com/tinylab/riscv-lab • ARM Lab – Learning embedded ARM software development，merged in Linux Lab Disk – https://gitee

with floating-point fallback Mykhailo Borovyk 🇺🇦 mbo@6it.dev Implementing support for RISC-V, including inline-asm Vladyslav Merais 🇺🇦 vmer@6it.dev Overall idea, and Insisting that 14/163 0/489 MSVC/x64 17/163 17/163 14/163 0/489 Apple Clang/ARM64 23/163 23/163 14/163 0/489 GCC/RISC-V 25/163 24/163 14/163 0/489 Tests: determinism failed / all testsPerformance: dmath&geometry tests_ 4.83x 1.89x 1.87x 1.33x 2.20x 1.31x Apple-Clang/ ARM64 5.54x 2.43x 3.09x 1.32x 2.47x 2.39x GCC/RISC-V 3.97x 3.07x 1.55x 1.10x 1.09x 1.10x Process-wide Deoptimizations — — No LTO — No fast-math, no

32bit 64bit 32bit 64bit Xx86 ARM RISC-V Xx86 ARM RISC-V (6) Following zero-overhead principle auto func (std: :Tanges: remainder ]}; 了] 了 y 一Range adaptorfor dlstributing work across tasks (CZ) ASM comparison > GCC RISC-V 64-bit assembly manual_loop(long，long): jsc-chunk_evenly (long，long): addiji sp

control,etc. Integrated ecosystems and extensive compatibility through distributed kits Arm, x86, RISC-V, SW-64, LoongArch, Power, 100+ servers, and 300+ cards CRM ERP BSS/OSS Edge/KubeEdge Developer support Scenario collaboration Scenario enablement Linux kernel x86, Arm, RISC-V GPU NPU Real-time kernel Security kernel Database Big data Resource orchestration Desktop system is read from or written to the memory, and streamlines data access. PC x86 Kunpeng Other chips RISC-V Data center NFV Database Virtualization Big data HPC 920 9XX GCC for openEuler Compilation

uint64_t v = 0x123456789abcdef0; 48 x86 movabs r10, 0x123456789abcdef0 49 ba f0 de bc 9a 78 56 34 12 RISC-V li a5, 305418240 addi a5, a5, 1657 li a0, -1698897920 slli a5, a5, 32 addi a0, a0, -272 add uint64_t v = 0x123456789abcdef0; 49 x86 movabs r10, 0x123456789abcdef0 49 ba f0 de bc 9a 78 56 34 12 RISC-V li a5, 305418240 addi a5, a5, 1657 li a0, -1698897920 slli a5, a5, 32 addi a0, a0, -272 add uint64_t v = 0x123456789abcdef0; 50 x86 movabs r10, 0x123456789abcdef0 49 ba f0 de bc 9a 78 56 34 12 RISC-V li a5, 305418240 addi a5, a5, 1657 li a0, -1698897920 slli a5, a5, 32 addi a0, a0, -272 add

responsibilities will be assigned per two years. 02 03 01 MULTIPLE ARCHITECT 14 ▹ x86_64 ▹ aarch64 ▹ RISC-V Idea Incubating 15 ▹ iSula ▹ StratoVirt ▹ A-Tune iSula + StratoVirt 16 K8s Docker QEMU Container secGear Framework 17 secGear Service Layer secGear Middleware Layer secGear Base Layer Intel SGX RISC-V Keystone ARM TrustZone secGear Enclave Unified APIs secGear Host Unified APIs 18 https://www

OF EDGE COMPUTING WEBASSEMBLY TINYGO PLAYGROUND PLAY.TINYGO.ORG DEMO RISC-V SIFIVE HIFIVE1 REV. B FREEDOM E310 RISC-V 32-BIT PROCESSOR 320 MHZ 4MB FLASH DEMO THE FUTURE IS HERE NOW. TINYGO