Accelerators(NPU)Search Space for TPU-like Specialized Accelerators Tensor Compute Primitives Unified Buffer Acc FIFO Explicitly Managed Memory Subsystem TPUsTensorization Challenge Compute primitives }
 def @te_add_one(%a: NDArray, %b: NDArray) { var %n %A = decl_buffer(shape=[%n], src=%a) %B = decl_buffer(shape=[%n], src=%b) for %i = 0 to 10 [data_par] { %B[%i] = %A[%i] Python Support @tvm.hybrid def te_add_one(a, b): n = var(“n”) A = bind_buffer(shape=[n], a) B = bind_buffer(shape=[n], b) for i in iter_range(n, iter_type=”data_par”): A[i] = B[i]

ReLU Bias ReLU Bias ReLU Bias ReLU Pooling Pooling Pooling Pooling Image Queue Instruction Buffer Cross Bar Pooling/ EWA© Copyright 2018 Xilinx Xilinx Edge DPU IP (DPUv2) Source: Published results

codegen 。Auto tune tiling sizes 。 Vectorized load/store for higher bandwidth utilization 。Double buffer to hide memory load latency 。 storage align to reduce bank conflicts of shared memory 。 Virtual